https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111153

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:fafd2502c5416fe4f69daf13224ab1efbf256a1c

commit r14-4086-gfafd2502c5416fe4f69daf13224ab1efbf256a1c
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Sun Sep 17 10:05:49 2023 +0800

    RISC-V: Support VLS modes reduction[PR111153]

    This patch supports VLS reduction vectorization.

    It can optimize the current reduction vectorization codegen with current
COST model.

    TYPE __attribute__ ((noinline, noclone))        \
    reduc_plus_##TYPE (TYPE * __restrict a, int n)          \
    {                                               \
      TYPE r = 0;                                   \
      for (int i = 0; i < n; ++i)                   \
        r += a[i];                                  \
      return r;                                     \
    }

      T (int32_t)                                   \

    TEST_PLUS (DEF_REDUC_PLUS)

    Before this patch:

            vle32.v v2,0(a5)
            addi    a5,a5,16
            vadd.vv v1,v1,v2
            bne     a5,a4,.L4
            lui     a4,%hi(.LC0)
            lui     a5,%hi(.LC1)
            addi    a4,a4,%lo(.LC0)
            vlm.v   v0,0(a4)
            addi    a5,a5,%lo(.LC1)
            andi    a1,a1,-4
            vmv1r.v v2,v3
            vlm.v   v4,0(a5)
            vcompress.vm    v2,v1,v0
            vmv1r.v v0,v4
            vadd.vv v1,v2,v1
            vcompress.vm    v3,v1,v0
            vadd.vv v3,v3,v1
            vmv.x.s a0,v3
            sext.w  a0,a0
            beq     a3,a1,.L12

    After this patch:

            vle32.v v2,0(a5)
            addi    a5,a5,16
            vadd.vv v1,v1,v2
            bne     a5,a4,.L4
            li      a5,0
            andi    a1,a1,-4
            vmv.s.x v2,a5
            vredsum.vs      v1,v1,v2
            vmv.x.s a0,v1
            beq     a3,a1,.L12

            PR target/111153

    gcc/ChangeLog:

            * config/riscv/autovec.md: Add VLS modes.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mode reduction
case.
            * gcc.target/riscv/rvv/autovec/vls/reduc-1.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-10.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-11.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-12.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-13.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-14.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-15.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-16.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-17.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-18.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-19.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-2.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-20.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-21.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-3.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-4.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-5.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-6.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-7.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-8.c: New test.
            * gcc.target/riscv/rvv/autovec/vls/reduc-9.c: New test.

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