[Bug target/110665] RISC-V do not preserve vector registers in interrupt handler

[lehua.ding at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110665

--- Comment #3 from Lehua Ding <lehua.ding at rivai dot ai> ---
Fixed by the commit
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=fdd59c0f73e9e681cd5f4d0eee2dd58d60d8dbe1

with compiler option --param=riscv-vector-abi.
Confirmed after support riscv-vector-abi in default.