https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111381
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The trunk branch has been updated by Lehua Ding <lh...@gcc.gnu.org>: https://gcc.gnu.org/g:68cb873fd360dbb64f2a6dfb28e79399ff99d07d commit r14-4008-g68cb873fd360dbb64f2a6dfb28e79399ff99d07d Author: Lehua Ding <lehua.d...@rivai.ai> Date: Thu Sep 14 23:35:42 2023 +0800 RISC-V: Support combine extend and reduce sum to widen reduce sum This patch add combine pattern to combine extend and reduce sum to widen reduce sum. The pattern in autovec.md was adjusted as needed. Note that the current vectorization cannot generate reduce operand which is LMUL=M8, because this means that we need an LMUL=M16 for the extended operand, which is currently not possible. So I've added VI_QHS_NO_M8 and VF_HS_NO_M8 mode iterator, which exclude mode which is LMUL=M8. PR target/111381 gcc/ChangeLog: * config/riscv/autovec-opt.md (*reduc_plus_scal_<mode>): New combine pattern. (*fold_left_widen_plus_<mode>): Ditto. (*mask_len_fold_left_widen_plus_<mode>): Ditto. * config/riscv/autovec.md (reduc_plus_scal_<mode>): Change from define_expand to define_insn_and_split. (fold_left_plus_<mode>): Ditto. (mask_len_fold_left_plus_<mode>): Ditto. * config/riscv/riscv-v.cc (expand_reduction): Support widen reduction. * config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM): Add new iterators and attrs. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: New test.
