[Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

[juzhe.zhong at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751

--- Comment #40 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
I try this following code to set ELSE_VALUE:

static tree
riscv_preferred_else_value (unsigned ifn, tree vectype, unsigned int nops,
                            tree *ops)
{
  if (riscv_v_ext_mode_p (TYPE_MODE (vectype)))
    {
      // return build_zero_cst (size_type_node);
      return get_or_create_ssa_default_def (cfun, create_tmp_var (vectype));
    }

  return default_preferred_else_value (ifn, vectype, nops, ops);
}

It generate the GIMPLE IR ELSE VALUE is an uninitialized value:

vector([128,128]) signed char D.2821;
vector([128,128]) signed char _72(D);
vect_patt_42.12_73 = .COND_LEN_MOD ({ -1, ... }, vect__3.8_67, vect__6.11_71,
_72(D), _82, 0);

Then "_72" is expanded into RTL as:

(reg:RVVM8QI 136 [ D.2821 ])

I try to use SSA_NAME_IS_DEFAULT_DEF to check whether this operand is 
the undef value since:

(gdb) p ops[4]->u->reg->attrs->decl->base.default_def_flag
$7 = 0

It's false that I can't recognize it as "undefine" value.