[Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

[jeremy.bennett at embecosm dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
Thanks @JuzheZhong,

I have tried again with the latest GCC and the problem has gone away.  This can
now be marked as fixed.