[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:6b96de22d6bcadb45530c1898b264e4738afa4fd

commit r14-3744-g6b96de22d6bcadb45530c1898b264e4738afa4fd
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Wed Sep 6 22:28:03 2023 +0800

    RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

    This patch fix incorrect mode tieable between DI and V2SI which cause ICE
    in RA.

    gcc/ChangeLog:

            PR target/111296
            * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode
            tieable for RVV modes.

    gcc/testsuite/ChangeLog:

            PR target/111296
            * g++.target/riscv/rvv/base/pr111296.C: New test.