https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111114
Bug ID: 111114
Summary: RISC-V: False combine extend + vcond_mask when modify
by vect_recog_over_widening_pattern
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: lehua.ding at rivai dot ai
Target Milestone: ---
The vect_recog_over_widening_pattern in vect pass will change:
v2 = EXTEND (v1)
v3 = VEC_COND_EXPR (mask, v2, { 1, 1, ... })
to:
v2 = VEC_COND_EXPR (mask, v1, { 1, 1, ... })
v3 = EXTEND (v2)
when it is safe. This change looks like no gain for riscv and makes it
impossible to combine them into a MASK_EXTEND in combine pass.
https://godbolt.org/z/PWE4rzr7j
