[Bug target/110985] RISC-V: Incorrect code gen for RVV VLS

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:685abdb4a1fe46a12da5cc9ae1d5aaef9344a339

commit r14-3173-g685abdb4a1fe46a12da5cc9ae1d5aaef9344a339
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Fri Aug 11 16:45:26 2023 +0800

    RISC-V: Fix vec_series expander[PR110985]

    This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985

    gcc/ChangeLog:
            PR target/110985
            * config/riscv/riscv-v.cc (expand_vec_series): Refactor the
expander.

    gcc/testsuite/ChangeLog:
            PR target/110985
            * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: New test.