https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91681
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Roger Sayle <sa...@gcc.gnu.org>: https://gcc.gnu.org/g:275a2124e4928c88bd5469096356ba393b6aadfb commit r14-2466-g275a2124e4928c88bd5469096356ba393b6aadfb Author: Roger Sayle <ro...@nextmovesoftware.com> Date: Wed Jul 12 14:14:15 2023 +0100 i386: Fix FAIL of gcc.target/i386/pr91681-1.c The recent change in TImode parameter passing on x86_64 results in the FAIL of pr91681-1.c. The issue is that with the extra flexibility, the combine pass is now spoilt for choice between using either the *add<dwi>3_doubleword_concat or the *add<dwi>3_doubleword_zext patterns, when one operand is a *concat and the other is a zero_extend. The solution proposed below is provide an *add<dwi>3_doubleword_concat_zext define_insn_and_split, that can benefit both from the register allocation of *concat, and still avoid the xor normally required by zero extension. I'm investigating a follow-up refinement to improve register allocation further by avoiding the early clobber in the =&r, and handling (custom) reloads explicitly, but this piece resolves the testcase failure. 2023-07-12 Roger Sayle <ro...@nextmovesoftware.com> gcc/ChangeLog PR target/91681 * config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): New define_insn_and_split derived from *add<dwi>3_doubleword_concat and *add<dwi>3_doubleword_zext.
