https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93768
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jan Beulich <jbeul...@gcc.gnu.org>: https://gcc.gnu.org/g:607613e516670dd817e7467e774ed2e3440bdb21 commit r14-2309-g607613e516670dd817e7467e774ed2e3440bdb21 Author: Jan Beulich <jbeul...@suse.com> Date: Wed Jul 5 09:40:40 2023 +0200 x86: use VPTERNLOG for further bitwise two-vector operations All combinations of and, ior, xor, and not involving two operands can be expressed that way in a single insn. gcc/ PR target/93768 * config/i386/i386.cc (ix86_rtx_costs): Further special-case bitwise vector operations. * config/i386/sse.md (*iornot<mode>3): New insn. (*xnor<mode>3): Likewise. (*<nlogic><mode>3): Likewise. (andor): New code iterator. (nlogic): New code attribute. (ternlog_nlogic): Likewise. gcc/testsuite/ PR target/93768 * gcc.target/i386/avx512-binop-not-1.h: New. * gcc.target/i386/avx512-binop-not-2.h: New. * gcc.target/i386/avx512f-orn-si-zmm-1.c: New test. * gcc.target/i386/avx512f-orn-si-zmm-2.c: New test.
