https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109907
--- Comment #17 from Georg-Johann Lay <gjl at gcc dot gnu.org> --- Created attachment 55129 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55129&action=edit Patch for AVR backend: combine patterns, "extzv<mode>", test case For now I have the attaches patch that resolves all cases of the included test-case. Iknow that the maintainers are not very fond of such combine patterns though... <log> Provide more patterns to improve extracting (negated) single bits. Deprecated insn "extzv" is replaced by "extzv<mode>". The patterns now also allow lower I/O memory because both the insns and the instructions for I/O like SBIC/SBIS and the ones for REGs like SBRC/SBRS. Even in the presence of "extzv<mode>" there is no canonical form for single bit extractions, even less for extracting the insersed bit. So more than one mathod is provided. gcc/ PR target/109907 * config/avr/avr-protos.h (avr_out_extr, avr_out_extr_not): New protos. * config/avr/avr.cc (avr_out_extr, avr_out_extr_not): New functions. (avr_adjust_insn_length) [ADJUST_LEN_EXTR_NOT, ADJUST_LEN_EXTR]: Handle cases. * config/avr/avr.md (adjust_len) [extr, extr_not]: Add to define_attr. (extzv): Turn into extzv<mode>. (MSB): New mode attribute. (*extzv_split, *extzv): Allow lower I/O addresses in operand 1. Unify constraints to a single case, as avr_out_extr() will now handle the alternatives. (*extzv.not_split, *extzv_not): New insn and its post-reload split. (*extzv.subreg.<mode>, *extzv.neg.subreg-msb.<mode>, *extzv<mode>.ge): New insns and post-reload splits. (*extzv.xor, *extzv.io.lsr): New insns and pre-reload split. * config/avr/constraints.md (Yil): New constraint for reg or low I/O. * config/avr/predicates.md (reg_or_low_io_operand, const7_operand) (const15_operand, const23_operand, const31_operand) (const_0_to_7_operand, const_0_to_15_operand, const_0_to_23_operand) (const_0_to_31_operand): New predicates. gcc/testsuite/ PR target/109907 * gcc.target/avr/pr109907.c: New test. </log>
