https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109272
Bug ID: 109272
Summary: RISCV: vbool*_t better opportunities of code
generation
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: pan2.li at intel dot com
Target Milestone: ---
Assume we have sample code as below.
#include "riscv_vector.h"
void
test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
vbool8_t v1 = *(vbool8_t*)in;
vbool16_t v2 = *(vbool16_t*)in;
*(vbool8_t*)(out + 100) = v1;
*(vbool16_t*)(out + 200) = v2;
}
It will generate the assembly code like
test_vbool8_then_vbool16:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
csrr a5,vlenb
slli a3,a3,1
add a3,a3,sp
addi a2,a1,100
srli a5,a5,3
vsetvli a4,zero,e8,m1,ta,ma
sub a5,a3,a5
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a5)
addi a1,a1,200
csrr t0,vlenb
vsetvli a3,zero,e8,mf2,ta,ma
slli t1,t0,1
vlm.v v24,0(a5)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
Actually we can optimize the generated code to:
test_vbool8_then_vbool4:
addi a3,a1,100
vsetvli a4,zero,e8,m1,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a3,zero,e8,mf2,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
