[Bug target/108654] Incorrect codegen of RVV GCC

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108654
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <k...@gcc.gnu.org>:

https://gcc.gnu.org/g:3a982e07d28a46da81ee5b65b03a896d84b32a48

commit r13-6826-g3a982e07d28a46da81ee5b65b03a896d84b32a48
Author: Pan Li <pan2...@intel.com>
Date:   Wed Mar 8 15:33:33 2023 +0800

    RISC-V: Bugfix for rvv bool mode size adjustment

    Fix the bug of the rvv bool mode size by the adjustment.
    Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64])
    of the vbool*_t, the mode size (aka byte size) will be adjusted to
    [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The
    adjustment will provide correct information for the underlying
    redundant instruction elimiation.

    Given the below sample code:
    {
      vbool1_t v1 = *(vbool1_t*)in;
      vbool64_t v2 = *(vbool64_t*)in;

      *(vbool1_t*)(out + 100) = v1;
      *(vbool64_t*)(out + 200) = v2;
    }

    Before the size adjustment:
    csrr    t0,vlenb
    slli    t1,t0,1
    csrr    a3,vlenb
    sub     sp,sp,t1
    slli    a4,a3,1
    add     a4,a4,sp
    addi    a2,a1,100
    vsetvli a5,zero,e8,m8,ta,ma
    sub     a3,a4,a3
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a2)
    vsm.v   v24,0(a3)
    addi    a1,a1,200
    csrr    t0,vlenb
    vsetvli a4,zero,e8,mf8,ta,ma
    slli    t1,t0,1
    vlm.v   v24,0(a3)
    vsm.v   v24,0(a1)
    add     sp,sp,t1
    jr      ra

    After the size adjustment:
    addi    a3,a1,100
    vsetvli a4,zero,e8,m8,ta,ma
    addi    a1,a1,200
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a3)
    vsetvli a5,zero,e8,mf8,ta,ma
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a1)
    ret

    Additionally, the size adjust cannot cover all possible combinations
    of the vbool*_t code pattern like above. We will take a look into it
    in another patches.

    PR 108185
    PR 108654

    gcc/ChangeLog:

            PR target/108654
            PR target/108185
            * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Adjust size
            for vector mask modes.
            * config/riscv/riscv.cc (riscv_v_adjust_bytesize): New.
            * config/riscv/riscv.h (riscv_v_adjust_bytesize): New.

    gcc/testsuite/ChangeLog:

            PR target/108654
            PR target/108185
            * gcc.target/riscv/rvv/base/pr108185-1.c: Update.
            * gcc.target/riscv/rvv/base/pr108185-2.c: Ditto.
            * gcc.target/riscv/rvv/base/pr108185-3.c: Ditto.

    Signed-off-by: Pan Li <pan2...@intel.com>
    Co-authored-by: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>