https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248
--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> --- (In reply to Jeffrey A. Law from comment #5) > So a datapoint in this effort. > > For the Veyron V1, all the bitmanip instructions except clmul and cpop are > single cycle and can be handled by any of the 4 standard ALUs. > > clmul, cpop are 4c and use the shared multi-cycle ALU. This is what I mostly expect for a standard core even. clmul and cpop would be very similar the mul instruction even. I hearing our core will be very similar (the core is still in design) but I will definitely be posting patches to make sure our core's cost model is correct and all once it is finished.
