https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
Alexander Monakov <amonakov at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |amonakov at gcc dot gnu.org
--- Comment #13 from Alexander Monakov <amonakov at gcc dot gnu.org> ---
Jakub, sorry if I misunderstood the patches from a brief glance, but what
ordering guarantees are you assuming for AVX accesses? It should not be
SEQ_CST. I think what Intel manual is saying is that said accessing will not
tear, but reordering is the same as pre-existing x86 TSO rules (a load can
finish before an earlier store is globally visible).
