https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602
--- Comment #10 from Vineet Gupta <vineetg at rivosinc dot com> ---
At expand time, RV backend was NOT creating REQ_EQUAL note for 1 << 38
(insn 8 7 9 2 (set (reg:DI 79)
(ashift:DI (reg:DI 78)
(const_int 38 [0x26]))) "../../../shifter.c":10:40 -1
However cse1 adds it anyways, so that was a false alarm.
(insn 8 7 9 2 (set (reg:DI 79)
(ashift:DI (reg:DI 78)
(const_int 38 [0x26]))) "../../../../shifter.c":10:40 159 {ashldi3}
(expr_list:REG_EQUAL (const_int 274877906944 [0x4000000000])
So when entering combine, we have following
(insn 6 3 7 2 (set (reg:DI 76)
(ashift:DI (reg/v:DI 74 [ a ])
(const_int 6 [0x6])))
(insn 7 6 8 2 (set (reg:DI 78)
(const_int 1 [0x1]))
(insn 8 7 9 2 (set (reg:DI 79)
(ashift:DI (reg:DI 78)
(const_int 38 [0x26])))
(expr_list:REG_EQUAL (const_int 274877906944 [0x4000000000])
(insn 9 8 10 2 (set (reg:DI 77)
(plus:DI (reg:DI 79)
(const_int -64 [0xffffffffffffffc0])))
(expr_list:REG_EQUAL (const_int 274877906880 [0x3fffffffc0])
(insn 10 9 15 2 (set (reg:DI 75)
(and:DI (reg:DI 76)
(reg:DI 77)))
Obviously the regular code flow can't merge/match 5.
The trailing note processing in combine replaces the pattern with available set
REG_EQUAL but it only handles two instructions at a time. This issue needs it
to handle three: insn 9, 10, 6
Perhaps we need to do the REQ_EQUAL note handling not seperately in the end,
but as part of each of 2 insn combine / 3 insn combine / 4 insn combine (after
the regular try_combine() fails for each of them ?
