https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106704
--- Comment #7 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Richard Biener from comment #3)
> get_vcond_icode (vmode=E_V8SFmode, cmode=E_V8SImode, uns=false) at
> /home/rguenther/src/trunk/gcc/optabs-query.h:117
>
> gets us CODE_FOR_nothing though, because
>
> 5168 enum insn_code
> 5169 raw_optab_handler (unsigned scode)
> 5170 {
> 5171 int i = lookup_handler (scode);
> 5172 return (i >= 0 && this_fn_optabs->pat_enable[i]
> 5173 ? pats[i].icode : CODE_FOR_nothing);
> (gdb) p i
> $12 = 313
> (gdb) p this_fn_optabs->pat_enable[i]
> $14 = false
> (gdb) p pats[i].icode
> $15 = CODE_FOR_vcondv8sfv8si
>
> #define HAVE_vcondv8sfv8si (TARGET_AVX2 \
> && (GET_MODE_NUNITS (V8SFmode) \
> == GET_MODE_NUNITS (V8SImode)))
>
> huh. Where's AVX2 coming from here ... ah, there's also
>
> (define_expand "vcond<V_256:mode><VI_256:mode>"
> [(set (match_operand:V_256 0 "register_operand")
> (if_then_else:V_256
> (match_operator 3 ""
> [(match_operand:VI_256 4 "nonimmediate_operand")
> (match_operand:VI_256 5 "general_operand")])
> (match_operand:V_256 1)
> (match_operand:V_256 2)))]
> "TARGET_AVX2
> && (GET_MODE_NUNITS (<V_256:MODE>mode)
> == GET_MODE_NUNITS (<VI_256:MODE>mode))"
> {
> bool ok = ix86_expand_int_vcond (operands);
> gcc_assert (ok);
> DONE;
> })
>
> that looks like a duplicate and that shadows(?) the earlier pattern?
> Hmm, or rather - are the patterns using the "wrong" modes? Should
> they be "vcond<V[IF]_256:mode><V_256:mode>" instead? I think so.
>
> @cindex @code{vcond@var{m}@var{n}} instruction pattern
> @item @samp{vcond@var{m}@var{n}}
> Output a conditional vector move. Operand 0 is the destination to
> receive a combination of operand 1 and operand 2, which are of mode @var{m},
> dependent on the outcome of the predicate in operand 3 which is a signed
> vector comparison with operands of mode @var{n} in operands 4 and 5. The
> modes @var{m} and @var{n} should have the same size. Operand 0
> will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
> where @var{msk} is computed by element-wise evaluation of the vector
> comparison with a truth value of all-ones and a false value of all-zeros.
there's 2 modes, var{n} is comparison mode, is mode of operands 4 and 5,
var{m} is mode of vector to be moved, is mode of operand 0, operand 1 and
operand 2, vcond<V_256:mode><VI_256:mode> should be right.
