[Bug target/103842] [12 regression] ICE on ilmbase-2.5.7: during RTL pass: expand

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103842

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>:

https://gcc.gnu.org/g:242783c52c22ed96eae722b2fa9847711ac84699

commit r12-6129-g242783c52c22ed96eae722b2fa9847711ac84699
Author: Jakub Jelinek <ja...@redhat.com>
Date:   Tue Dec 28 10:58:43 2021 +0100

    i386: Fix handling of SUBREGs in divv2sf3 [PR103842]

    register_operand predicate allows not just REGs, but also SUBREGs of REGs,
    and for the latter lowpart_subreg might FAIL when trying to create
paradoxical
    SUBREG in some cases.  For the input operand fixed by force_reg on it
first,
    for the output operand handled by always dividing into a fresh V4SFmode
temporary
    and emit_move_insn into the destination afterwards, that is also beneficial
for
    combine.

    2021-12-28  Jakub Jelinek  <ja...@redhat.com>

            PR target/103842
            * config/i386/mmx.md (divv2sf3): Use force_reg on op1.  Always
perform
            divv4sf3 into a pseudo and emit_move_insn into operands[0].

            * g++.dg/opt/pr103842.C: New test.