https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102627
--- Comment #4 from Vladimir Makarov <vmakarov at gcc dot gnu.org> --- (In reply to Jakub Jelinek from comment #3) > The assembly difference r11-8007 to r11-8008 is: > --- pr102627.s 2021-10-06 06:32:46.000000000 -0400 > +++ pr102627.s 2021-10-06 06:33:00.000000000 -0400 > @@ -77,10 +77,10 @@ main: > movq %rdx, %rcx > movq %rax, %rdx > movq e(%rip), %rax > - movq %rcx, 8(%rsp) > + movl %ecx, 12(%rsp) > movzbl f(%rip), %ecx > salq %cl, %rax > - movq 8(%rsp), %rcx > + movl 12(%rsp), %ecx > movq %rax, %rsi > movl $0, %edi > call w > I believe y returns the 128-bit struct g return value in %rdx:%rax pair, > right before the above instructions, and the above change means that instead > of spilling the whole 64-bits of %rcx that holds at that point u.j and u.k > members (u.k in the upper 32 bits of %rcx) it spills just 32-bits of %ecx > and fills it back in, effectively setting u.k to 0. The w call then takes > %rdi, %rsi arguments it doesn't use and the TImode in %rcx:%rdx pair, but > with the high 32 bits of the TImode value lost. The reason for the spill is > clear, the shift instruction needs that register... Jakub, thank you for the analysis. I believe the patch in question just triggered a bug in hard reg live range splitting. I am working on the PR. I hope to fix it on this week or at begining of the next week.
