https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102177
Bug ID: 102177
Summary: Implement C++17 P0418R2
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c++
Assignee: unassigned at gcc dot gnu.org
Reporter: jakub at gcc dot gnu.org
Target Milestone: ---
I think we aren't implementing https://wg21.link/p0418r2
which dropped the requirement that failure mode can't be stronger than success
mode.
For
long
bar (long *x, long y, long z)
{
__atomic_compare_exchange_n (x, &y, z, 0, __ATOMIC_RELAXED,
__ATOMIC_SEQ_CST);
return y;
}
we warn:
warning: failure memory model cannot be stronger than success memory model for
‘__atomic_compare_exchange’ [-Winvalid-memory-model]
and document it in doc/extend.texi:
Otherwise, @code{false} is returned and memory is affected according
to @var{failure_memorder}. This memory order cannot be
@code{__ATOMIC_RELEASE} nor @code{__ATOMIC_ACQ_REL}. It also cannot be a
stronger order than that specified by @var{success_memorder}.
and libstdc++ has:
__glibcxx_assert(__b2 <= __b1);
in various spots in bits/atomic_base.h.
Do we emit right code on aarch64 and other weak ordering targets for this case
despite the warning?
