[Bug target/102154] [12 Regression] ICE in extract_insn, at recog.c:2769 since r12-3277-gd2874d905647a1d146dafa60199d440e837adc4d

[crazylht at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102154

--- Comment #10 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #9)
> > 
> > (define_insn "movsf_hardfloat"
> >   [(set (match_operand:SF 0 "nonimmediate_operand"
> >      "=!r,       f,         v,          wa,        m,         wY,
> >       Z,         m,         wa,         !r,        f,         wa,
> >       !r,        *c*l,      !r,         *h")
> >     (match_operand:SF 1 "input_operand"
> >      "m,         m,         wY,         Z,         f,         v,
> >       wa,        r,         j,          j,         f,         wa,
> >       r,         r,         *h,         0"))]
> >   "(register_operand (operands[0], SFmode)
> >    || register_operand (operands[1], SFmode))
> >    && TARGET_HARD_FLOAT
> >    && (TARGET_ALLOW_SF_SUBREG
> >        || valid_sf_si_move (operands[0], operands[1], SFmode))"
> > 
> > Oh, The pattern disllow sf subreg.
> 
> Here TARGET_ALLOW_SF_SUBREG || valid_sf_si_move (operands[0], operands[1],
> SFmode) is false, others are true which means input_operand accept
> (subreg:SF (reg:DI 4))

And w/ -mpower10 (subreg:SF (reg:DI 4) 0) can be handled by reload to

(insn 6 3 16 2 (set (mem/c:SF (plus:DI (reg/f:DI 1 1)
                (const_int -16 [0xfffffffffffffff0])) [4 %sfp+48 S4 A32])
        (reg:SF 3 3 [orig:120+4 ] [120]))
"/export/users2/liuhongt/tools-build/build_intel-innersource_ppc_debug/test.c":7:13
567 {movsf_hardfloat}
     (nil))
(insn 16 6 11 2 (set (reg:SF 33 1 [orig:117 <retval> ] [117])
        (mem/c:SF (plus:DI (reg/f:DI 1 1)
                (const_int -16 [0xfffffffffffffff0])) [4 %sfp+48 S4 A32]))
"/export/users2/liuhongt/tools-build/build_intel-innersource_ppc_debug/test.c":7:13
567 {movsf_hardfloat}