[Bug middle-end/102133] [12 Regression] ICE in set_rtl building libgcc __muldc3 for 32-bit SPARC

[crazylht at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102133

--- Comment #6 from Hongtao.liu <crazylht at gmail dot com> ---
The difference of insn sequence is like
good one:
(insn 5 4 6 (clobber (reg/v:DF 153))
"/scratch/jmyers/glibc/many12/src/gcc/libgcc/libgcc2.c":1948:1 -1
     (nil))

(insn 6 5 7 (set (subreg:SI (reg/v:DF 153) 4)
        (mem/c:SI (plus:SI (reg/f:SI 103 virtual-incoming-args)
                (const_int 28 [0x1c])) [1 d+4 S4 A32]))
"/scratch/jmyers/glibc/many12/src/gcc/libgcc/libgcc2.c":1948:1 -1
     (nil))

(insn 7 6 0 (set (subreg:SI (reg/v:DF 153) 0)
        (mem/c:SI (plus:SI (reg/f:SI 103 virtual-incoming-args)
                (const_int 24 [0x18])) [1 d+0 S4 A32]))
"/scratch/jmyers/glibc/many12/src/gcc/libgcc/libgcc2.c":1948:1 -1
     (nil))

(reg/v:DF 153)

bad one:

(insn 5 4 6 (clobber (reg:DI 154))
"/scratch/jmyers/glibc/many12/src/gcc/libgcc/libgcc2.c":1948:1 -1
     (nil))

(insn 6 5 7 (set (subreg:SI (reg:DI 154) 4)
        (mem/c:SI (plus:SI (reg/f:SI 103 virtual-incoming-args)
                (const_int 28 [0x1c])) [1 d+4 S4 A32]))
"/scratch/jmyers/glibc/many12/src/gcc/libgcc/libgcc2.c":1948:1 -1
     (nil))

(insn 7 6 0 (set (subreg:SI (reg:DI 154) 0)
        (mem/c:SI (plus:SI (reg/f:SI 103 virtual-incoming-args)
                (const_int 24 [0x18])) [1 d+0 S4 A32]))
"/scratch/jmyers/glibc/many12/src/gcc/libgcc/libgcc2.c":1948:1 -1
     (nil))

(subreg:DF (reg:DI 154) 0)


and subreg hit gcc_assert in set_rtl.