https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101796
Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Last reconfirmed| |2021-08-27 Severity|normal |enhancement Component|rtl-optimization |target Status|UNCONFIRMED |NEW Ever confirmed|0 |1 --- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> --- Combine is able to do the combine but it fails as it does not match: Trying 10, 9 -> 14: 10: r92:HI=0x3 9: r91:V32HI=vec_duplicate(r92:HI) REG_DEAD r92:HI REG_EQUAL const_vector 14: r88:V32HI=r96:V8DI#0 0>>r91:V32HI REG_DEAD r96:V8DI REG_DEAD r91:V32HI Failed to match this instruction: (set (reg:V32HI 88) (lshiftrt:V32HI (subreg:V32HI (reg:V8DI 96) 0) (const_vector:V32HI [ (const_int 3 [0x3]) repeated x32 ]))) This instruction does not have alt for the dup/const_vect case I think: (define_insn "<avx2_avx512>_<insn>v<mode><mask_name>" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (any_lshift:VI2_AVX512VL (match_operand:VI2_AVX512VL 1 "register_operand" "v") (match_operand:VI2_AVX512VL 2 "nonimmediate_operand" "vm")))] "TARGET_AVX512BW" "vp<vshift>v<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseishft") (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) Note I don't think simplify-rtx will change const_vector to just 3 though.