https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101611
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |ASSIGNED
--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
--- gcc/config/i386/sse.md.jj 2021-07-22 12:37:20.439532859 +0200
+++ gcc/config/i386/sse.md 2021-07-24 18:03:07.328126900 +0200
@@ -20499,13 +20499,34 @@ (define_expand "vlshr<mode>3"
(match_operand:VI48_256 2 "nonimmediate_operand")))]
"TARGET_AVX2")
-(define_expand "vashr<mode>3"
- [(set (match_operand:VI8_256_512 0 "register_operand")
- (ashiftrt:VI8_256_512
- (match_operand:VI8_256_512 1 "register_operand")
- (match_operand:VI8_256_512 2 "nonimmediate_operand")))]
+(define_expand "vashrv8di3"
+ [(set (match_operand:V8DI 0 "register_operand")
+ (ashiftrt:V8DI
+ (match_operand:V8DI 1 "register_operand")
+ (match_operand:V8DI 2 "nonimmediate_operand")))]
"TARGET_AVX512F")
+(define_expand "vashrv4di3"
+ [(set (match_operand:V4DI 0 "register_operand")
+ (ashiftrt:V4DI
+ (match_operand:V4DI 1 "register_operand")
+ (match_operand:V4DI 2 "nonimmediate_operand")))]
+ "TARGET_AVX2"
+{
+ if (!TARGET_AVX512VL)
+ {
+ rtx mask = ix86_build_signbit_mask (V4DImode, 1, 0);
+ rtx t1 = gen_reg_rtx (V4DImode);
+ rtx t2 = gen_reg_rtx (V4DImode);
+ rtx t3 = gen_reg_rtx (V4DImode);
+ emit_insn (gen_vlshrv4di3 (t1, operands[1], operands[2]));
+ emit_insn (gen_vlshrv4di3 (t2, mask, operands[2]));
+ emit_insn (gen_xorv4di3 (t3, t1, t2));
+ emit_insn (gen_subv4di3 (operands[0], t3, t2));
+ DONE;
+ }
+})
+
(define_expand "vashr<mode>3"
[(set (match_operand:VI12_128 0 "register_operand")
(ashiftrt:VI12_128
@@ -20527,12 +20548,12 @@ (define_expand "vashr<mode>3"
}
})
-(define_expand "vashrv2di3<mask_name>"
+(define_expand "vashrv2di3"
[(set (match_operand:V2DI 0 "register_operand")
(ashiftrt:V2DI
(match_operand:V2DI 1 "register_operand")
(match_operand:V2DI 2 "nonimmediate_operand")))]
- "TARGET_XOP || TARGET_AVX512VL"
+ "TARGET_XOP || TARGET_AVX2"
{
if (TARGET_XOP)
{
@@ -20541,6 +20562,18 @@ (define_expand "vashrv2di3<mask_name>"
emit_insn (gen_xop_shav2di3 (operands[0], operands[1], neg));
DONE;
}
+ if (!TARGET_AVX512VL)
+ {
+ rtx mask = ix86_build_signbit_mask (V2DImode, 1, 0);
+ rtx t1 = gen_reg_rtx (V2DImode);
+ rtx t2 = gen_reg_rtx (V2DImode);
+ rtx t3 = gen_reg_rtx (V2DImode);
+ emit_insn (gen_vlshrv2di3 (t1, operands[1], operands[2]));
+ emit_insn (gen_vlshrv2di3 (t2, mask, operands[2]));
+ emit_insn (gen_xorv2di3 (t3, t1, t2));
+ emit_insn (gen_subv2di3 (operands[0], t3, t2));
+ DONE;
+ }
})
(define_expand "vashrv4si3"
