https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101076
--- Comment #2 from Coco Wang <wf831130 at sina dot com> ---
(In reply to Andrew Pinski from comment #1)
> What target is this for?
> For both x86_64 and aarch64 we have both shifts in SI mode so we don't end
> up with problem.
> We get the following RTL for aarch64 (before combine):
> (insn 6 3 7 2 (set (reg:SI 96)
> (ashift:SI (reg/v:SI 94 [ a ])
> (const_int 16 [0x10]))) "t551.c":3:15 692
> {*aarch64_ashl_sisd_or_int_si3}
> (expr_list:REG_DEAD (reg/v:SI 94 [ a ])
> (nil)))
> (insn 7 6 12 2 (set (reg:SI 95)
> (ashiftrt:SI (reg:SI 96)
> (const_int 16 [0x10]))) "t551.c":3:22 696
> {*aarch64_ashr_sisd_or_int_si3}
> (expr_list:REG_DEAD (reg:SI 96)
> (nil)))
>
> And then we get:
> Trying 6 -> 7:
> 6: r96:SI=r97:SI<<0x10
> REG_DEAD r97:SI
> 7: r95:SI=r96:SI>>0x10
> REG_DEAD r96:SI
> Successfully matched this instruction:
> (set (reg:SI 95)
> (sign_extend:SI (subreg:HI (reg:SI 97) 0)))
> In combine.
>
>
> I Noticed you have:
> r76:SI=r78:DI#0<<0x10
> 7: r75:SI=r76:SI>>0x10
>
> In combine, so you have a subreg of r78, where is the subreg produced ...
The target is RISCV64, I will check the reason why there is a subreg produced.
