https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100637
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Uros Bizjak <u...@gcc.gnu.org>: https://gcc.gnu.org/g:46ca31d65092e5afcef292f807fcf14c5363280d commit r12-883-g46ca31d65092e5afcef292f807fcf14c5363280d Author: Uros Bizjak <ubiz...@gmail.com> Date: Tue May 18 17:25:54 2021 +0200 i386: Implement 4-byte vector support [PR100637] Add infrastructure, logic and arithmetic support for 4-byte vectors. These can be used with SSE2 targets, where movd instructions from/to XMM registers are available. x86_64 ABI passes 4-byte vectors in integer registers, so also add logic operations with integer registers. 2021-05-18 Uroš Bizjak <ubiz...@gmail.com> gcc/ PR target/100637 * config/i386/i386.h (VALID_SSE2_REG_MODE): Add V4QI and V2HI modes. (VALID_INT_MODE_P): Ditto. * config/i386/mmx.md (VI_32): New mode iterator. (mmxvecsize): Handle V4QI and V2HI. (Yv_Yw): Ditto. (mov<VI_32:mode>): New expander. (*mov<mode>_internal): New insn pattern. (movmisalign<VI_32:mode>): New expander. (neg<VI_32:mode>): New expander. (<plusminus:insn><VI_32:mode>3): New expander. (*<plusminus:insn><VI_32:mode>3): New insn pattern. (mulv2hi3): New expander. (*mulv2hi3): New insn pattern. (one_cmpl<VI_32:mode>2): New expander. (*andnot<VI_32:mode>3): New insn pattern. (<any_logic:code><VI_32:mode>3): New expander. (*<any_logic:code><VI_32:mode>3): New insn pattern. gcc/testsuite/ PR target/100637 * gcc.target/i386/pr100637-1b.c: New test. * gcc.target/i386/pr100637-1w.c: Ditto. * gcc.target/i386/pr92658-avx2-2.c: Do not XFAIL scan for pmovsxbq. * gcc.target/i386/pr92658-avx2.c: Do not XFAIL scan for pmovzxbq. * gcc.target/i386/pr92658-avx512vl.c: Do not XFAIL scan for vpmovdb. * gcc.target/i386/pr92658-sse4-2.c: Do not XFAIL scan for pmovsxbd and pmovsxwq. * gcc.target/i386/pr92658-sse4.c: Do not XFAIL scan for pmovzxbd and pmovzxwq.
