https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
Priority|P3 |P2
Last reconfirmed| |2021-04-16
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Confirmed.
#1 0x0000000001d9f1c5 in gen_movdi (operand0=0x7ffff63ae390,
operand1=0x7ffff63ae480)
at /home/rguenther/src/trunk/gcc/config/arm/arm.md:6187
6187 gcc_checking_assert (aligned_operand (operands[1], DImode));
(gdb) p debug_rtx (operands[1])
(mem/u/c:DI (reg/f:SI 114) [0 S8 A32])
I think the bug is that
/* Use the subreg machinery either to narrow OP0 to the required
words or to cope with mode punning between equal-sized modes.
In the latter case, use subreg on the rhs side, not lhs. */
rtx sub;
HOST_WIDE_INT regnum;
poly_uint64 regsize = REGMODE_NATURAL_SIZE (GET_MODE (op0));
if (known_eq (bitnum, 0U)
&& known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (op0))))
{
sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0);
if (sub)
{
if (reverse)
sub = flip_storage_order (GET_MODE (op0), sub);
here simplify_gen_subreg simplifies (subreg:DI ((mem/u/c:SC (reg/f:SI 114) [0
S8 A32])) to (mem/u/c:DI (reg/f:SI 114) [0 S8 A32]) but SCmode has
different alignment requirement than DImode.
