https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97249
--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #1)
> for i386 backend, maybe we can adjust pattern of
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 934b60a288f..2bfa9635fab 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -17658,12 +17658,7 @@ (define_expand "<code>v32qiv32hi2"
> (define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"
> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
> (any_extend:V8HI
> - (vec_select:V8QI
> - (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
> - (parallel [(const_int 0) (const_int 1)
> - (const_int 2) (const_int 3)
> - (const_int 4) (const_int 5)
> - (const_int 6) (const_int 7)]))))]
> + (subreg:V8HI(match_operand:V16QI 1 "register_operand" "Yr,*x,v")
> 0)))]
> "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
> "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> [(set_attr "isa" "noavx,noavx,avx")
Correct typo
@@ -17658,12 +17658,7 @@ (define_expand "<code>v32qiv32hi2"
(define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"
[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
(any_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
- (parallel [(const_int 0) (const_int 1)
- (const_int 2) (const_int 3)
- (const_int 4) (const_int 5)
- (const_int 6) (const_int 7)]))))]
+ (subreg:V8HI (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
> 0)))]
