https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96861
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed| |2020-08-31
Keywords| |missed-optimization
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Collected chain #1...
insns: 6
defs to convert: r84, r85
Computing gain for chain #1...
Instruction gain 8 for 6: {r84:SI=smax(r85:SI,0x1);clobber flags:CC;}
REG_DEAD r85:SI
REG_UNUSED flags:CC
Instruction conversion gain: 8
Registers conversion cost: 4
Total gain: 4
Converting chain #1...
else if (GET_CODE (src) == SMAX
|| GET_CODE (src) == SMIN
|| GET_CODE (src) == UMAX
|| GET_CODE (src) == UMIN)
{
/* We do not have any conditional move cost, estimate it as a
reg-reg move. Comparisons are costed as adds. */
igain += m * (COSTS_N_INSNS (2) + ix86_cost->add);
/* Integer SSE ops are all costed the same. */
igain -= ix86_cost->sse_op;
}
is a bit of hand-waving, esp. since costs in general have not been
very consistent between the GPR and vector parts of the cores
(that also hurts vector cost estimates btw which also compare those
apples vs. oranges)
