https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70053
luoxhu at gcc dot gnu.org changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |segher at gcc dot gnu.org
--- Comment #7 from luoxhu at gcc dot gnu.org ---
When expanding "D.2914.td0 = c_5(D);" in expand_assignment (to=<component_ref
0x7ffff55909c0>, from=<ssa_name 0x7ffff5390b40>, nontemporal=false) at
../../gcc-master/gcc/expr.c:5058
1) expr.c:5158: to_rtx = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_WRITE);
gdb pr to_rtx
(mem/c:BLK (reg/f:DI 112 virtual-stack-vars) [2 D.2914+0 S32 A128])
...
2) expr.c:5167: to_rtx = adjust_address (to_rtx, mode1, 0);
p mode1
$86 = E_TDmode
(gdb) pr to_rtx
(mem/c:TD (reg/f:DI 112 virtual-stack-vars) [2 D.2914+0 S16 A128])
to_rtx is generated with address conversion from DImode to TDmode here.
...
3) expr.c:5374: result = store_field (to_rtx, bitsize,
bitpos,bitregion_start, bitregion_end, mode1, from, get_alias_set (to),
nontemporal, reversep);
then the assignment instruction is generated as below:
(insn 11 10 12 4 (set (mem/c:TD (reg/f:DI 112 virtual-stack-vars) [1
D.2914.td0+0 S16 A128]) (reg/v:TD 121 [ c ])) "pr70053.c":20:14 -1 (nil))
So if we need remove the redundant store/load in expand, the conversion from
DImode to TDmode should be avoided for this case when using virtual-stack-vars
registers. (For PR65421, there are similar DImode to DFmode conversion).
pr70053.c.236r.expand with -O2:
1: NOTE_INSN_DELETED
6: NOTE_INSN_BASIC_BLOCK 2
2: r119:TD=%2:TD
3: r120:TD=%4:TD
4: r121:TD=%6:TD
5: NOTE_INSN_FUNCTION_BEG
8: r122:CCFP=cmp(r120:TD,r121:TD)
9: pc={(r122:CCFP!=0)?L16:pc}
REG_BR_PROB 708669604
10: NOTE_INSN_BASIC_BLOCK 4
11: [r112:DI]=r121:TD
12: r123:DI=r112:DI+0x10
13: [r123:DI]=r121:TD
14: pc=L21
15: barrier
16: L16:
17: NOTE_INSN_BASIC_BLOCK 5
18: [r112:DI]=r119:TD
19: r124:DI=r112:DI+0x10
20: [r124:DI]=r120:TD
21: L21:
22: NOTE_INSN_BASIC_BLOCK 6
23: r125:TD=[r112:DI]
24: r127:DI=r112:DI+0x10
25: r126:TD=[r127:DI]
26: r117:TD=r125:TD
27: r118:TD=r126:TD
31: %2:TD=r117:TD
32: %4:TD=r118:TD
33: use %2:TD
34: use %4:TD
