https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94613
--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Andreas Krebbel <kreb...@gcc.gnu.org>: https://gcc.gnu.org/g:2930bb321794c241d8df5591a5bf447bf89c6e82 commit r10-7827-g2930bb321794c241d8df5591a5bf447bf89c6e82 Author: Andreas Krebbel <kreb...@linux.ibm.com> Date: Mon Apr 20 19:36:33 2020 +0200 PR94613: Fix vec_sel builtin for IBM Z The vsel instruction is a bit-wise select instruction. Using an IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being generated in the combine pass. With the patch the pattern is written using bit operations. However, I've just noticed that the manual still demands a fixed point mode for AND/IOR and friends although several targets emit bit ops on floating point vectors (including i386, Power, and s390). So I assume this is a safe thing to do?! gcc/ChangeLog: 2020-04-20 Andreas Krebbel <kreb...@linux.ibm.com> PR target/94613 * config/s390/s390-builtin-types.def: Add 3 new function modes. * config/s390/s390-builtins.def: Add mode dependent low-level builtin and map the overloaded builtins to these. * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ... ("vsel<V_HW"): ... this and rewrite the pattern with bitops. gcc/testsuite/ChangeLog: 2020-04-20 Andreas Krebbel <kreb...@linux.ibm.com> PR target/94613 * gcc.target/s390/zvector/pr94613.c: New test. * gcc.target/s390/zvector/vec_sel-1.c: New test.
