https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Max Filippov <jcmvb...@gcc.gnu.org>: https://gcc.gnu.org/g:a288e202c5e50704968685fc2922d159335be2cb commit r10-7728-ga288e202c5e50704968685fc2922d159335be2cb Author: Max Filippov <jcmvb...@gmail.com> Date: Mon Apr 13 13:26:04 2020 -0700 xtensa: fix PR target/94584 Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can load value from memory, but they don't treat volatile memory correctly. Add %v1 before load instructions to emit 'memw' instruction when -mserialize-volatile is in effect. 2020-04-14 Max Filippov <jcmvb...@gmail.com> gcc/ * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2) (extendhisi2_internal): Add %v1 before the load instructions. gcc/testsuite/ * gcc.target/xtensa/pr94584.c: New test.
