[Bug target/93937] New: Variable vector extract & zero extend insn can never match

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93937

            Bug ID: 93937
           Summary: Variable vector extract & zero extend insn can never
                    match
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org
  Target Milestone: ---

In looking at the variable vector extract code, the insns that attempt to merge
a zero extend with a variable extract of a vector element will never match:

(define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
        (zero_extend:<VS_scalar>
         (unspec:<VSX_EXTRACT_I:VS_scalar>
          [(match_operand:VSX_EXTRACT_I 1 "input_operand" "v,v,Q")
           (match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
          UNSPEC_VSX_EXTRACT)))
   (clobber (match_scratch:DI 3 "=r,r,&b"))
   (clobber (match_scratch:V2DI 4 "=X,&v,X"))]
  "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
  "#"
  "&& reload_completed"
  [(const_int 0)]
{
  machine_mode smode = <VS_scalar>mode;
  rs6000_split_vec_extract_var (gen_rtx_REG (smode, REGNO (operands[0])),
                                operands[1], operands[2],
                                operands[3], operands[4]);
  DONE;
}
  [(set_attr "isa" "p9v,*,*")])

It will never match, because the compiler will never generate code of the form:

(set (reg:SI)
     (zero_extend:SI
      (unspec:SI [(reg:V4SI)
                  (reg:DI)] UNSPEC_VSX_EXTRACT)))

I.e. the zero_extend type should be DImode.  Obviously the issue with PR
target/93932 (using input_operand) will also apply to this insn, once the modes
are fixed.