https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93455
Bug ID: 93455
Summary: aarch64: Q constraint address is recomputed
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: nsz at gcc dot gnu.org
Target Milestone: ---
gcc may recompute the address used in a Q constraint
(which may be used for atomic load and stores).
static volatile int x[1];
int f()
{
int r;
asm volatile ("A %w0 %1" : "=r"(r) : "Q"(*x));
asm volatile ("B %0" : "=Q"(*x));
return r;
}
with -O3 gcc generates
f:
adrp x1, .LANCHOR0
add x0, x1, :lo12:.LANCHOR0
A w0 [x0]
add x1, x1, :lo12:.LANCHOR0
B [x1]
ret
i expected one address computation.
