https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91927
--- Comment #2 from Guillaume <gr.audio at gmail dot com> --- Thanks for your quick reply. Yes, I actually managed to write a minimal test case showing the problem (attached source file). Compiling it with: aarch64-elf-gcc -mcpu=cortex-a72 -march=armv8-a+crc -O3 -mstrict-align -S Unaligned_Access.c I get the following assembly code: ------------------------------------------------------------ TestCase: cbz x0, .L7 stp x29, x30, [sp, -48]! mov x29, sp str x19, [sp, 16] mov x19, x0 add x0, sp, 32 str xzr, [sp, 32] str wzr, [sp, 40] bl SetTag ldr d0, [sp, 36] str d0, [x19, 8] ldr x19, [sp, 16] ldp x29, x30, [sp], 48 ret ------------------------------------------------------------ As can be seen here, an "ldr d0, [sp, 36]" instruction is emitted, which is a 64-bit transfer on an address aligned to 4-byte, but not aligned to 8-byte (sp + 36). This particular test case doesn't seem to generate a problem with -O2, only with -O3, but my own code did. With -O2, it emits "ldp w1, w0, [sp, 36]" instead of " ldr d0, [sp, 36]", which I believe should be aligned? I didn't find how to show the same behavior with -O2 as happens with -O3, with a simple test case, so far, so you may add to the report that the problem with -O2 is unconfirmed. Thanks for your time, Le sam. 28 sept. 2019 à 00:53, pinskia at gcc dot gnu.org < gcc-bugzi...@gcc.gnu.org> a écrit : > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91927 > > --- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> --- > Do you have a full testcase? > > -- > You are receiving this mail because: > You reported the bug.
