https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176
--- Comment #27 from Maciej W. Rozycki <ma...@linux-mips.org> --- Yes, it is the same problem, the same address calculation occurs here, and the lack of 32-bit address space wraparound is a part of the n32 Linux ABI, which implies support for processors that do not support such a wraparound in hardware (no CP0.Status.PX bit). You may try experimenting with ISA/ASE selection options, so that LWX is not considered a valid instruction by GCC. Otherwise I can't help with finding a workaround as I don't know one offhand and I'm not involved with MIPS development anymore, sorry. And neither is Doug BTW. This really ought to be fixed properly in GCC.
