[Bug target/83250] _mm256_zextsi128_si256 missing for AVX2 zero extension

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83250

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2019-08-05
     Ever confirmed|0                           |1

--- Comment #4 from H.J. Lu <hjl.tools at gmail dot com> ---
This compiles:

---
#include <immintrin.h>

__m256i
_mm256_zextsi128_si256 (__m128i x)
{
  return __extension__ (__m256i) { x[0], x[1], 0, 0 };
}

__m512i
_mm512_zextsi256_si512 (__m256i x)
{
  return __extension__ (__m512i) { x[0], x[1], x[2], x[3],
                                   0, 0, 0, 0 };
}

__m512i
_mm512_zextsi128_si512 (__m128i x)
{
  return _mm512_zextsi256_si512 (_mm256_zextsi128_si256 (x));
}
---

But combiner doesn't convert nested vec_concat into a single vec_concat:

Trying 12 -> 14: 
   12: r94:V4DI=vec_concat(r96:V2DI,const_vector)
      REG_DEAD r96:V2DI
   14: r87:V8DI=vec_concat(r94:V4DI,const_vector)
      REG_DEAD r94:V4DI
Failed to match this instruction:
(set (reg:V8DI 87) 
    (vec_concat:V8DI (vec_concat:V4DI (reg:V2DI 96) 
            (const_vector:V2DI [
                    (const_int 0 [0]) repeated x2
                ]))
        (const_vector:V4DI [
                (const_int 0 [0]) repeated x4
            ])))

Also we don't have patterns for AVX/AVX512 instructions with zero
extension, like

(set (reg:V4DI 91)
    (vec_concat:V4DI (subreg:V2DI (plus:V16QI (subreg:V16QI (reg:V2DI 97) 0)
                (subreg:V16QI (reg:V2DI 96) 0)) 0)
        (const_vector:V2DI [
                (const_int 0 [0]) repeated x2
            ])))