https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91124
--- Comment #10 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
The execution failures are a different bug.
Patterns like:
(define_insn "sse2_cvttpd2dq<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_concat:V4SI
(fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm"))
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2 && <mask_avx512vl_condition>"
{
if (TARGET_AVX)
return "vcvttpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
else
return "cvttpd2dq\t{%1, %0|%0, %1}";
}
are correct when not masked, but for masked the RTL representation is wrong:
(define_insn ("sse2_cvttpd2dq_mask")
[
(set (match_operand:V4SI 0 ("register_operand") ("=v"))
(vec_merge:V4SI (vec_concat:V4SI (fix:V2SI (match_operand:V2DF 1
("vector_operand") ("vBm")))
(const_vector:V2SI [
(const_int 0 [0])
(const_int 0 [0])
]))
(match_operand:V4SI 2 ("nonimm_or_0_operand") ("0C"))
(match_operand:QI 3 ("register_operand") ("Yk"))))
] ("(TARGET_AVX512F) && (TARGET_SSE2 && TARGET_AVX512VL)") ("*{
if (TARGET_AVX)
return "vcvttpd2dq{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}";
else
return "cvttpd2dq\t{%1, %0|%0, %1}";
}")
because it doesn't for the _mask but not _maskz case actually represent what
the instruction does. The instruction zeros up bits 64 and up in the vector
(DEST[MAX_VL-1:VL/2] <- 0;, no matter what is in the upper bits of DEST before
when it is masked off.
Working on another patch.
