https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89021
--- Comment #6 from hjl at gcc dot gnu.org <hjl at gcc dot gnu.org> --- Author: hjl Date: Wed May 15 15:02:54 2019 New Revision: 271213 URL: https://gcc.gnu.org/viewcvs?rev=271213&root=gcc&view=rev Log: i386: Allow MMX register modes in SSE registers In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386-c.c (ix86_target_macros_internal): Define __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. * config/i386/i386.c (ix86_set_reg_reg_cost): Add support for TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE. (ix86_vector_mode_supported_p): Likewise. * config/i386/i386.h (TARGET_MMX_WITH_SSE): New. Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386-c.c trunk/gcc/config/i386/i386.c trunk/gcc/config/i386/i386.h