https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90088
Bug ID: 90088
Summary: 3 ops LEA should be avoided on Intel CPUs
Product: gcc
Version: 9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: nok.raven at gmail dot com
Target Milestone: ---
Target: Intel x86
Originally I filed a bug report to LLVM about
int foo(int x)
{
return (x << 1) | 1;
}
But got an answered that 3 ops LEA is intentionally avoided due to
> For LEA instructions with three source operands and some specific
> situations, instruction latency has increased to 3 cycles, and must
> dispatch via port 1:
> — LEA that has all three source operands: base, index, and offset.
> — LEA that uses base and index registers where the base is EBP, RBP, or R13.
> — LEA that uses RIP relative addressing mode.
> — LEA that uses 16-bit addressing mode.
From 3.5.1.3 (Using LEA) of Intel's Optimization Reference Manual.
https://godbolt.org/z/OqkdAO
