https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86965
Bug ID: 86965
Summary: nios2 optimizer forgets about known upper bits of
register
Product: gcc
Version: 8.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: already5chosen at yahoo dot com
Target Milestone: ---
Created attachment 44545
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=44545&action=edit
source code that demonstrates my case
Target: nios2-elf
Configured with: ../gcc-8.2.0/configure \
--target=nios2-elf \
--prefix=/home/m/opt/cross \
--disable-nls \
--enable-languages=c,c++ \
--without-headers \
--enable-multiarch
Thread model: single
gcc version 8.2.0 (GCC)
I am not sure if two cases in my report are related to each other. To me it
looks like they are since both cases appear related to optimizer losing track
of known state of upper 24 bits of register.
I know that bug writing guidelines discourage inclusion of the content of the
object file, but I made an effort to make it as short as possible. It really
looks like the only sane way to report.
00000000 <good1>:
0: 20c00007 ldb r3,0(r4)
4: 18bff404 addi r2,r3,-48
8: 28800015 stw r2,0(r5)
c: 18801960 cmpeqi r2,r3,101
10: 18c01120 cmpeqi r3,r3,68
14: 10c4b03a or r2,r2,r3
18: f800283a ret
0000001c <bad1>:
1c: 20800003 ldbu r2,0(r4)
20: 10c03fcc andi r3,r2,255
24: 18c0201c xori r3,r3,128
28: 18ffe004 addi r3,r3,-128
2c: 18fff404 addi r3,r3,-48
30: 108037cc andi r2,r2,223
34: 28c00015 stw r3,0(r5)
38: 10801160 cmpeqi r2,r2,69
3c: f800283a ret
#-- comments:
bad1 should generate approximately the same code as good1.
7 instructions instead of 9
Or, if compiler really wants to be smart, it can generate 6 instructions:
ldb r2,0(r4)
addi r3,r2,-48
stw r3,0(r5)
andi r2,r2,223 ; sign extension in bits[31..24] does not matter!
cmpeqi r2,r2,69
ret
#-- end of comments:
00000040 <good2>:
40: 21800007 ldb r6,0(r4)
44: 30c00b60 cmpeqi r3,r6,45
48: 31800ae0 cmpeqi r6,r6,43
4c: 28c00015 stw r3,0(r5)
50: 1986b03a or r3,r3,r6
54: 20c5883a add r2,r4,r3
58: f800283a ret
0000005c <bad2>:
5c: 21800007 ldb r6,0(r4)
60: 30c00b60 cmpeqi r3,r6,45
64: 31800ae0 cmpeqi r6,r6,43
68: 18803fcc andi r2,r3,255 # this instruction serves no purpose
6c: 1986b03a or r3,r3,r6
70: 28800115 stw r2,4(r5)
74: 28800015 stw r2,0(r5)
78: 20c5883a add r2,r4,r3
7c: f800283a ret
#-- comments:
bad2 should be identical to good2 except of addition of the second store.
#-- end of comments:
