https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85610
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |missed-optimization
Target| |x86_64-*-*, i?86-*-*
Status|UNCONFIRMED |NEW
Last reconfirmed| |2018-05-03
Component|tree-optimization |target
Version|tree-ssa |7.3.1
Ever confirmed|0 |1
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Confirmed. RTL expansion looks ok so it looks like a combine/backend issue.
;; _5 = __atomic_load_1 (&MEM[(const struct __atomic_base *)&flag_atomic]._M_i,
0);
(insn 5 4 0 (set (reg:QI 87 [ _5 ])
(mem/v:QI (symbol_ref:DI ("flag_atomic") [flags 0x2] <var_decl
0x7ffff665d360 flag_atomic>) [-1 S1 A8]))
"/usr/include/c++/7/bits/atomic_base.h":396 -1
(nil))
;; if (_5 == 0)
(insn 6 5 7 (set (reg:CCZ 17 flags)
(compare:CCZ (reg:QI 87 [ _5 ])
(const_int 0 [0]))) "t.C":9 -1
(nil))
(jump_insn 7 6 0 (set (pc)
(if_then_else (ne (reg:CCZ 17 flags)
(const_int 0 [0]))
(label_ref 0)
(pc))) "t.C":9 -1
(int_list:REG_BR_PROB 5400 (nil)))
