[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512

--- Comment #6 from ktkachov at gcc dot gnu.org ---
The right-shift SIMD instructions don't allow a shift of zero. The
left-shifting ones do.

So I'd expect *aarch64_lshr_sisd_or_int_<mode>3 needs to be adjusted as well