https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83402
--- Comment #15 from pc at gcc dot gnu.org --- Author: pc Date: Mon Apr 23 21:14:38 2018 New Revision: 259582 URL: https://gcc.gnu.org/viewcvs?rev=259582&root=gcc&view=rev Log: rs6000: Fix _mm_slli_epi{32,64} for shift values 16 through 31 and negative (PR84302) The powerpc versions of _mm_slli_epi32 and __mm_slli_epi64 in emmintrin.h do not properly handle shift values between 16 and 31, inclusive. These are setting up the shift with vec_splat_s32, which only accepts *5 bit signed* shift values, or a range of -16 to 15. Values above 15 produce an error: error: argument 1 must be a 5-bit signed literal Fix is to effectively reduce the range for which vec_splat_s32 is used to < 32 and use vec_splats otherwise. Also, __mm_slli_epi{16,32,64}, when given a negative shift value, should always return a vector of {0}. PR target/83402 * config/rs6000/emmintrin.h (_mm_slli_epi{16,32,64}): Ensure that vec_splat_s32 is only called with 0 <= shift < 16. Ensure negative shifts result in {0}. gcc/testsuite/ PR target/83402 * gcc.target/powerpc/sse2-psllw-1.c: Refactor and add tests for several values: positive, negative, and zero. * gcc.target/powerpc/sse2-pslld-1.c: Same. * gcc.target/powerpc/sse2-psllq-1.c: Same. Modified: branches/ibm/gcc-7-branch/gcc/ChangeLog branches/ibm/gcc-7-branch/gcc/config/rs6000/emmintrin.h branches/ibm/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c branches/ibm/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c branches/ibm/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c
