https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82518
--- Comment #23 from Nick Clifton <nickc at redhat dot com> --- Hi Guys, >> But, as you have just discovered, (r5 + 12) is not 64-bit aligned... > > But from ARMv7 onwards it only has to be 4-byte aligned, which it is. And > this > code was build for cortex-a9, which is ARMv7-a. Ok, so this is a simulator bug. Aldy - these easiest thing for now would be to unilaterally relax the alignment test in Handle_Store_Double and see if that allows you to get further with your tests. (But yes, I agree, a reduced testcase would be a much better help than all this mucking about in the simulator). Cheers Nick
