https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83488
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |kyukhin at gcc dot gnu.org,
| |uros at gcc dot gnu.org
--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Perhaps it would help if we did:
--- gcc/config/i386/i386.opt.jj 2017-12-20 13:01:04.000000000 +0100
+++ gcc/config/i386/i386.opt 2017-12-20 15:18:59.351758063 +0100
@@ -726,15 +726,15 @@ Target Report Mask(ISA_AVX512VBMI) Var(i
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and
AVX512VBMI built-in functions and code generation.
mavx5124fmaps
-Target Report Mask(ISA_AVX5124FMAPS) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
AVX5124FMAPS built-in functions and code generation.
mavx5124vnniw
-Target Report Mask(ISA_AVX5124VNNIW) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
AVX5124VNNIW built-in functions and code generation.
mavx512vpopcntdq
-Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_AVX512VPOPCNTDQ) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
AVX512VPOPCNTDQ built-in functions and code generation.
mavx512vbmi2
@@ -742,7 +742,7 @@ Target Report Mask(ISA_AVX512VBMI2) Var(
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
AVX512VBMI2 built-in functions and code generation.
mavx512vnni
-Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_AVX512VNNI) Var(ix86_isa_flags2) Save
Support AVX512VNNI built-in functions and code generation.
mfma
@@ -774,11 +774,11 @@ Target Report Mask(ISA_POPCNT) Var(ix86_
Support code generation of popcnt instruction.
msgx
-Target Report Mask(ISA_SGX) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
Support SGX built-in functions and code generation.
mrdpid
-Target Report Mask(ISA_RDPID) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save
Support RDPID built-in functions and code generation.
mgfni
@@ -786,7 +786,7 @@ Target Report Mask(ISA_GFNI) Var(ix86_is
Support GFNI built-in functions and code generation.
mvaes
-Target Report Mask(ISA_VAES) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save
Support VAES built-in functions and code generation.
mvpclmulqdq
@@ -806,7 +806,7 @@ Target Report Mask(ISA_LZCNT) Var(ix86_i
Support LZCNT built-in function and code generation.
mhle
-Target Report Mask(ISA_HLE) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save
Support Hardware Lock Elision prefixes.
mrdseed
@@ -858,7 +858,7 @@ Target Report Mask(ISA_TBM) Var(ix86_isa
Support TBM built-in functions and code generation.
mcx16
-Target Report Mask(ISA_CX16) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save
Support code generation of cmpxchg16b instruction.
msahf
@@ -866,7 +866,7 @@ Target Report Mask(ISA_SAHF) Var(ix86_is
Support code generation of sahf instruction in 64bit x86-64 code.
mmovbe
-Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save
Support code generation of movbe instruction.
mcrc32
@@ -939,15 +939,15 @@ Target Report Mask(ISA_RTM) Var(ix86_isa
Support RTM built-in functions and code generation.
mmpx
-Target Report Mask(ISA_MPX) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_MPX) Var(ix86_isa_flags2) Save
Support MPX code generation.
mmwaitx
-Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save
Support MWAITX and MONITORX built-in functions and code generation.
mclzero
-Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save
Support CLZERO built-in functions and code generation.
mpku
@@ -1000,7 +1000,7 @@ Support Control-flow Enforcment Technol
and code generation.
mibt
-Target Report Mask(ISA_IBT) Var(ix86_isa_flags2) Save
+Target Report Mask(ISA2_IBT) Var(ix86_isa_flags2) Save
Specifically enables an indirect branch tracking feature from Control-flow
Enforcment Technology (CET).
and adjusted all uses, then it would be from the OPTION_MASK_* name clear which
bitmask we are talking about, we could more easily verify we don't mix the
non-compatible ones etc. Uros/Kyrill, what do you think? I'll certainly
bootstrap/regtest the above patch with the added testcase without this, this is
something that can be done incrementally.
