https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81357
--- Comment #12 from Qing Zhao <qing.zhao at oracle dot com> --- > Well it is not wrong, just non-optimal. It is possible to use a single > register > here but it means teaching GCC that these values are identical, which is > non-trivial as it likely affects various places in the mid-end (this issue is > target-independent). does “these values are identical” mean that the value “fParm + 1” and its zero_extension “unsigned long long (fParm +1)” are identical? I don’t think so. However, I do agree that there is opportunity for more compact code: these two values can be stored in the same register on some of the target. (for example, aarch64 or ia64). but Not on all the targets (for example, all 32bit targets). So, if we really want this additional optimization, this looks like a target-dependent one. we might add a new target-depend hook on whether two values with different width can be stored in the same register (one is the other one’s zero-extension), and then enhance register allocation with this hook?
