https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660
--- Comment #11 from Eric Botcazou <ebotcazou at gcc dot gnu.org> --- > The key (I think) is that the following sequence of 3 instructions ends up > being combined into 1 but the resulting instruction leaves the upper 32-bits > of reg 316 entirely undefined. Eventually this leads to reg 316 being > spilled to the stack where it is allocated a 64-bit slot but this spill only > writes 32-bits whereas consumers read 64-bit and even if the value will only > ever be operated on as 32-bit or less then logical and branch operations on > the reloaded value will go wrong and normal 32-bit operations will be > (strictly) undefined. But MIPS defines LOAD_EXTEND_OP so the 32 upper bits are defined, aren't they? Maybe the load sign-extends instead of zero-extending as specified initially.
