https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70961
--- Comment #5 from Wilco <wdijkstr at arm dot com> ---
As for a simple example, Proc_4 in Dhrystone is a good one. With -O2 and
-fno-rename-registers I get the following on Thumb-2:
000000c8 <Proc_4>:
c8: b430 push {r4, r5}
ca: f240 0300 movw r3, #0
ce: f240 0400 movw r4, #0
d2: f2c0 0300 movt r3, #0
d6: f2c0 0400 movt r4, #0
da: f240 0100 movw r1, #0
de: 681a ldr r2, [r3, #0]
e0: f2c0 0100 movt r1, #0
e4: 7824 ldrb r4, [r4, #0]
e6: 2542 movs r5, #66 ; 0x42
e8: 700d strb r5, [r1, #0]
ea: 2c41 cmp r4, #65 ; 0x41
ec: bf08 it eq
ee: f042 0201 orreq.w r2, r2, #1
f2: 601a str r2, [r3, #0]
f4: bc30 pop {r4, r5}
f6: 4770 bx lr
With -frename-registers:
000000c8 <Proc_4>:
c8: b430 push {r4, r5}
ca: f240 0300 movw r3, #0
ce: f240 0400 movw r4, #0
d2: f2c0 0300 movt r3, #0
d6: f2c0 0400 movt r4, #0
da: f240 0100 movw r1, #0
de: 681a ldr r2, [r3, #0]
e0: f2c0 0100 movt r1, #0
e4: f894 c000 ldrb.w ip, [r4]
e8: 2542 movs r5, #66 ; 0x42
ea: 700d strb r5, [r1, #0]
ec: f1bc 0f41 cmp.w ip, #65 ; 0x41
f0: bf08 it eq
f2: f042 0201 orreq.w r2, r2, #1
f6: 601a str r2, [r3, #0]
f8: bc30 pop {r4, r5}
fa: 4770 bx lr
So here it changed 2 16-bit instructions into 32-bit ones by changing R4 to IP.
However there is no benefit in doing so as it doesn't remove a move or create
additionally scheduling opportunities (the first liverange of R4 has only a
single use, so when it goes dead it is actually best to reuse R4 rather than
use a different register).
