[Bug target/69551] Wrong code with single element vector insert

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69551

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|middle-end                  |target

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
So we go the store_field path in expand_assignment with to_rtx being a V4SI reg
which ends up using the vec_set_optab producing this code:

  /* Use vec_set patterns for inserting parts of vectors whenever
     available.  */
  if (VECTOR_MODE_P (GET_MODE (op0))
      && !MEM_P (op0)
      && optab_handler (vec_set_optab, GET_MODE (op0)) != CODE_FOR_nothing
      && fieldmode == GET_MODE_INNER (GET_MODE (op0))
      && bitsize == GET_MODE_UNIT_BITSIZE (GET_MODE (op0))
      && !(bitnum % GET_MODE_UNIT_BITSIZE (GET_MODE (op0))))
    {
      struct expand_operand ops[3];
      machine_mode outermode = GET_MODE (op0);
      machine_mode innermode = GET_MODE_INNER (outermode);
      enum insn_code icode = optab_handler (vec_set_optab, outermode);
      int pos = bitnum / GET_MODE_BITSIZE (innermode);

      create_fixed_operand (&ops[0], op0);
      create_input_operand (&ops[1], value, innermode);
      create_integer_operand (&ops[2], pos);
      if (maybe_expand_insn (icode, 3, ops))
        return true;